The present invention relates to a method for the manufacture of a thin film field effect transistor of the type with self-alignment of the electrodes. This method applies to the large surface or area microelectronics field and in particular to the control and addressing of a liquid crystal flat screen or an image sensor. It can also be used in the production of rapid switching devices for integration on large surfaces.
Thin film silicon is at present the most widely developed method used for large surface electronic devices. The silicon is then used in amorphous or polycrystalline form. Most research carried out at present deals with the thin film MISFET transistor. For large surface applications, it is necessary for the thin film transistors (TFT) to have minimum response time. In the case of amorphous silicon, whose limited carrier mobility is known, the working frequencies are presently limited to a few hundred kHz. Moreover, when using this material, the saturation currents are low, so that the application of such transistors remains limited to the point-by-point addressing of a liquid crystal screen. For applications such as the peripheral control of a display screen or a shift register, higher working frequencies are required, as are higher saturation currents. In order to achieve these results, it is necessary to surmount certain technical constraints. The channel lengths must be reduced to the minimum, in order to minimize the transit time and the trapping of carriers. Particularly in the case of amorphous silicon, it is preferable to choose large channel widths in order to obtain high saturation currents. The thin film semiconductor and the gate insulant must be consecutively deposited and in the same deposition device, in order to preserve a good quality of the semiconductor - insulant interface. It is necessary to have good source and drain contacts. In the case of thin film devices produced on large surfaces, it is often indispensable to use an electrode self-alignment technology.
The presently developed transistors of the TFT type have a channel length of approximately 10 .mu.m, with or without self-alignment of the source and drain electrodes with respect to the gate. Smaller channel lengths have been obtained. In decreasing order, reference can be made to 8 .mu.m for a channel width W of 100 .mu.m (Y. OKUBO et al, SID 82 Digest, p. 40), 7 .mu.m for W=45 .mu.m (M. YAMANO et al, Japan Display 83, p. 356), said two transistors being intended for the matrix addressing of a liquid crystal screen. Reference can also be made to a transistor with a 3 .mu.m channel length and intended for an image sensor (A. J. SNELL et al, Journal of Non-Crystl.Sol. 59 and 60, 1983, p. 1211). In these three cases, the transistors have been produced with a gate below using conventional photolithography processes.
In conventional photogravure production processes the widths of the channels are dependent on their lengths. The greatest width obtained is approximately 1500 .mu.m for a length of 10 .mu.m (K. SUZUKI et al, SID 83 Digest, p. 146). Widths between 100 and 400 .mu.m are encountered in the case of amorphous silicon. Beyond this, technical difficulties occur which are linked with the actual procedure, such as resolution of the masks and alignment machines, superimposing, definition of etching action etc.
In order to obviate these disadvantages, the present invention proposes a method for the collective manufacture of transistors of the TFT type with a submicron gate self-aligned with the source and drain. Typically, the channel length will be between 0.5 and 1 .mu.m. Such an amorphous silicon transistor permits use up to frequencies of a few dozen megahertz. If the transistor is made from polycrystalline silicon, the maximum frequency of use can be extended to a few hundred megahertz. This type of transistor is used in faster large surface electronics.